What we supply
Tecsply supplies rigid multilayer PCBs from 8 to 40+ layers and up to 6.0 mm finished thickness, in six construction families, as bare boards for your EMS to assemble. Each board is quoted from a stackup that names the laminate, glass style and copper weight of every layer, and lead time is quoted per stackup.
| Construction | Range | Typical use |
|---|---|---|
| Rigid multilayer | 8–40+ layers · ≤ 6.0 mm | AI baseboards, switches, backplanes, test boards |
| HDI | 1+N+1 to any-layer | Fine-pitch BGA breakout, substrate-like PCBs |
| Sequential lamination | Multiple sub-cores | Blind and buried vias, back-drill-sensitive channels |
| Low-loss laminate builds | M6 · M7 · M8 grade | 56G, 112G and 224G PAM4 channels |
| Low-CTE reinforced | T-glass / NE-glass | Packages over 60 mm, thick boards |
| Heavy copper | 2–6 oz | Rack power shelves, busbar boards |
By layer count: 12 to 40+ layers
Layer count follows from routing density, lane count and power delivery, and total thickness follows from layer count. The table gives the starting points our stackup selector uses; the final count and thickness are set in the stackup review.
| Layer range | Typical boards | Typical thickness | First design limit |
|---|---|---|---|
| 12–18 layers | Avionics and defense boards (10–20 layers), smaller accelerator and controller boards, the low end of switch boards | 2.0–3.6 mm | Impedance on thin signal dielectrics; Class 3 plated-hole reliability on aerospace builds |
| 20–28 layers (incl. 22 and 24) | AI accelerator baseboards, 800G–1.6T switches and NICs (18–28 layers) | 2.4–4.5 mm (to 5.0 mm under packages over 60 mm) | Channel loss, fiber-weave skew and package warpage |
| 30–40+ layers | Backplanes and midplanes, the largest accelerator boards, semiconductor test boards | Up to 6.0 mm | Aspect ratio, back-drill stubs and plated-hole reliability |
12 to 18 layers
In this range most dielectrics sit in the thin and standard bands, 0.06–0.50 mm, and controlled-impedance pairs run on 1078, 1080 or 2113 glass. A 16-layer board with 2-ply 2116 cores, single-ply 1078 prepreg, 1 oz outer and ½ oz inner copper comes out at roughly 2.5 mm before plating, about 10:1 aspect ratio with a 0.25 mm finished hole. Aerospace boards in this range are built to IPC-6012 Class 3 on high-Tg, CAF-resistant laminate.
20 to 28 layers, including 22- and 24-layer boards
This is the core range for AI accelerator baseboards and cluster switches. A 24-layer AI baseboard has many dielectric layers between power and ground planes rather than under high-speed pairs, so we quote the signal layers in the grade the fastest lane needs (M7 for 112G, M8 for 224G) and the plane layers in a lower grade from a compatible family. Under packages larger than 60 mm the count rises toward 32 layers and the thickness toward 5.0 mm, and T-glass in the outer cores under the package limits warpage.
30 to 40+ layers
At 30 to 40+ layers boards reach 5 to 6 mm, and the drill becomes the constraint. Plan plated through-holes at about 10:1 for standard plating, so a 5.0 mm board needs a 0.50 mm drilled hole; 12:1 to 14:1 is advanced capability to confirm with the fabricator, and beyond that the design moves to back-drilled, blind or sequentially laminated vias. On boards this thick, z-axis expansion of the laminate stretching the copper barrels is the main reliability risk, so the laminate's z-axis CTE and Td are specified alongside its loss grade, and IST is the usual qualification test. See AI server PCB testing.
Backplanes for 56G and 112G PAM4
A communication backplane or midplane carries long channels between connectors across a thick board, which makes it a 30–40+ layer, 5–6 mm build in which loss, via stubs and plated-hole reliability all decide the stackup. A 38-layer backplane for 56G PAM4, for example, sits at the top of this range.
- 56G PAM4 (Nyquist 13.3 GHz): M6-grade laminate (Megtron 6 class) with NE-glass or L-glass in 1078 or 1080 style on the signal layers.
- 112G PAM4 (Nyquist 26.6 GHz): M7-grade laminate (Megtron 7, Tachyon 100G or EM-890K class) with spread NE-glass or L-glass in 1067 or 1078 style.
- 224G PAM4 (Nyquist 53.1 GHz): M8-grade laminate (Megtron 8, EM-892K or Astra MT77 class), 1027 or 1037 spread glass and HVLP3 or better foil; PTFE on channels over 25 cm.
- Planes and power: thick 7628 multi-ply cores and heavier copper carry the planes, often in a lower loss grade than the signal layers.
- Via stubs: state the maximum remaining back-drill stub and the must-not-cut layer on the drawing for every high-speed net; IPC-6012E leaves the limit to the procurement documents.
Copper foil is chosen per channel length on 56G and 112G layers. On a long 112G channel, a smoother foil can recover more loss than a laminate upgrade; the copper foil guide shows the numbers.
ATE and semiconductor test boards
ATE load boards, probe interface boards and other semiconductor test boards are high-layer-count PCBs that combine the hard parts of AI and backplane boards: dense, fine-pitch device fields that need HDI or sequential lamination for breakout, thick constructions where aspect ratio decides which drill sizes are realistic, controlled impedance on high-speed paths, and flatness across the device area. Tecsply supplies them as bare boards within the same 8 to 40+ layer, up to 6.0 mm envelope, built to your stackup and drawing. Send the stackup, the drill table with the smallest drilled hole, impedance targets and flatness requirements; aspect ratios above about 10:1 are reviewed with the fabricator before the quote. Components, sockets and hardware are fitted by your EMS or test-hardware assembler.
HDI and sequential lamination
Where through-holes cannot do the job, a high-layer-count board adds HDI structures, from 1+N+1 to any-layer, or sequential lamination of several sub-cores. Microvia dielectrics use the ultra-thin band, 0.03–0.06 mm, on 1027, 1037, 1067 or 106 glass, and sub-cores sit in the thin band. Each additional lamination cycle repeats the press, drill, plate and imaging steps for one sub-core, so cost and schedule rise with every cycle and the laminate must be rated for the number of laminations planned. Sequential lamination earns its cost under fine-pitch packages and on high-speed nets that need short via stubs without back-drilling. We count the lamination cycles in the stackup review because each one is also a schedule decision.
Materials: laminate, glass cloth, foil and thickness
Two material decisions set most of a high-layer-count board's behavior: the copper clad laminate loss grade, and the glass cloth inside it, where T-glass controls warpage and NE-glass controls loss and skew. Dielectric thickness per layer follows from the glass style and resin content, and conductor loss on 112G and 224G layers from the copper foil grade. Current allocation of these materials is tracked in the supply watch.
Before you send a stackup, add up its cores, prepreg plies and copper weights in the stackup calculator to see the total thickness and the aspect ratio of your smallest hole, and run your longest lane through the loss budget estimator.
What to send for a quote
A high-layer-count quote is only as good as the stackup behind it, so send the board, not just the Gerbers. We return a stackup with named CCL and glass constructions and a landed DDP price; lead time is quoted per stackup.
| Prototype | High volume, in addition |
|---|---|
| Gerber or ODB++ files and the fabrication drawing | Annual volume and release quantities |
| Stackup: laminate, glass style and copper weight per layer, or the targets to build to | Panel or array drawing |
| Drill table with the smallest drilled hole, back-drill and via structure | Test and report requirements written on the drawing |
| Impedance targets, IPC-6012 class and surface finish | Packaging and delivery point for the DDP price |
| Fastest lane rate, largest package, operating environment | Required country of manufacture and origin records |
| Quantity and required date | Qualified alternate laminate, if you have one |
Do not send ITAR-controlled technical data through the website, by email or by any other channel: Tecsply cannot accept ITAR-controlled data today. The readiness pre-check runs in your browser and the quote package tool combines tool results into one request.
What ships with every board
Every Tecsply PCB order ships with 4 records: the signed stackup, a material declaration down to glass style, copper weight and copper foil grade, inspection records to the specified IPC-6012 class, and country-of-origin records for the board, the laminate and the copper foil. AI compute boards are limited first by channel loss and package warpage, aerospace boards by z-axis expansion and Class 3 reliability; see AI compute and aerospace and defense.
High-layer-count PCB FAQ
Five questions buyers ask before sending a high-layer-count board for a quote; the full list is on the FAQ page.
How many layers can a high-layer-count PCB from Tecsply have?
Tecsply supplies rigid multilayer PCBs from 8 to 40+ layers and up to 6.0 mm finished thickness, as bare boards. Typical starting points are 16–24 layers at 2.4–3.6 mm for AI accelerator baseboards (20–32 layers at 3.2–5.0 mm when the package is larger than 60 mm), 18–28 layers at 3.0–4.5 mm for 800G–1.6T switches, 10–20 layers at 2.0–3.2 mm for avionics and defense boards, and 30–40+ layers up to 6.0 mm for backplanes and midplanes. A build thicker than 6.0 mm goes to an engineering review before it is quoted. Final layer count, thickness and lead time are quoted per stackup.
What does a 56G or 112G PAM4 backplane PCB need?
A backplane carries long channels between connectors across a thick board, so loss, via stubs and plated-hole reliability set the stackup. Our default starting points are an M6-grade laminate (Megtron 6 class) with NE-glass or L-glass in 1078 or 1080 style for 56G PAM4, and an M7-grade laminate (Megtron 7, Tachyon 100G or EM-890K class) with spread NE-glass or L-glass in 1067 or 1078 style for 112G PAM4, with the copper foil grade chosen per channel length. Thick 7628 multi-ply cores carry the planes, which is how 30–40+ layer backplanes reach 5 to 6 mm. On the drawing, state the maximum back-drill stub and the must-not-cut layer for high-speed nets, the impedance targets, and the laminate's z-axis expansion and Td. Plan plated through-holes at about 10:1 aspect ratio, so a 5.0 mm board needs a 0.50 mm drilled hole; higher ratios are confirmed with the fabricator.
Does Tecsply supply ATE load boards and semiconductor test boards?
Yes, as bare boards built to your stackup and drawing, within the same 8 to 40+ layer, up to 6.0 mm envelope as our other high-layer-count PCBs. Test boards combine dense, fine-pitch device fields that need HDI or sequential lamination for breakout, thick constructions where aspect ratio decides which drill sizes are realistic, controlled impedance on high-speed paths, and flatness across the device area. Send the stackup, the drill table with the smallest drilled hole, impedance targets and flatness requirements; aspect ratios above about 10:1 are reviewed with the fabricator before the quote. Tecsply does not assemble boards: components, sockets and hardware are fitted by your EMS or test-hardware assembler.
What should I send for a high-layer-count PCB quote, prototype or high volume?
For a prototype, send Gerber or ODB++ files, the fabrication drawing, the stackup (laminate, glass style and copper weight per layer, or the targets to build to), the drill table with back-drill and via structures, impedance targets, IPC-6012 class, surface finish, the fastest lane rate and largest package, quantity and required date. For high volume, add annual volume and release quantities, the panel or array drawing, the test and report requirements written on the drawing, packaging, the delivery point for the DDP price, and the country of manufacture you require. Every Tecsply product, from multilayer PCBs to machined metal parts, is manufactured in a non-restricted country specified by the customer. Lead time is quoted per stackup. Do not send ITAR-controlled technical data; Tecsply cannot accept it today.
Can Tecsply quote an ITAR-controlled PCB?
Not today. Tecsply cannot accept ITAR-controlled technical data, so please do not send ITAR-controlled drawings, Gerbers, stackups or specifications through the website, by email or by any other channel. For a defense program whose board data is not export-controlled, we quote through the normal process, with country-of-origin records for the board, the laminate and the copper foil. Every Tecsply product, from multilayer PCBs to machined metal parts, is manufactured in a non-restricted country specified by the customer.
Send the board, not just the Gerbers
Share the layer count, fastest lane rate, largest package, operating environment and annual volume; we return a stackup with named CCL and glass constructions and a landed DDP price.
References
- Panasonic MEGTRON 6(N) / 7(N) / 8(N), Isola Tachyon 100G / Astra MT77 and EMC EM-890K / EM-892K supplier datasheets.
- IPC-6012E sections 1.4.1, 1.4.2 and 3.3.9 (back-drilled holes); IPC-2226A (HDI structures); IPC-TM-650 2.6.26A (IST).
- Resonac MCL, Isola 370HR and Panasonic MEGTRON 6(N) construction tables: pressed thickness by glass style.