Foil roughness matters because current rides the surface
At high frequency, current in a trace crowds into a skin a fraction of a micron deep, and a rough foil makes that current follow every tooth of the surface profile. The skin depth in copper is about 2.09 / √f µm, so it falls from 0.92 µm at the 10G NRZ Nyquist frequency to 0.29 µm at 224G PAM4. Once the foil's roughness is larger than the skin depth, conductor loss rises by up to about 2×, the ceiling of the Hammerstad–Jensen roughness model.
| Lane rate (Nyquist) | Skin depth | Standard ED Rq 2.0 µm | RTF Rq 1.0 µm | VLP Rq 0.7 µm | HVLP Rq 0.45 µm | HVLP3 Rq 0.25 µm |
|---|---|---|---|---|---|---|
| 10G NRZ (5.2 GHz) | 0.92 µm | 1.90 | 1.65 | 1.43 | 1.21 | 1.07 |
| 56G PAM4 (13.3 GHz) | 0.57 µm | 1.96 | 1.85 | 1.72 | 1.45 | 1.17 |
| 112G PAM4 (26.6 GHz) | 0.41 µm | 1.98 | 1.93 | 1.85 | 1.67 | 1.31 |
| 224G PAM4 (53.1 GHz) | 0.29 µm | 1.99 | 1.96 | 1.92 | 1.82 | 1.52 |
The table shows 2 things. At 10G, even a mid-grade foil keeps the penalty moderate, so standard or RTF foil is the economical choice. At 112G and 224G, anything rougher than HVLP-class foil is already near the 2× ceiling, and only the smoothest grades still buy back loss.
Foil grades compared
Foil grades are named by the profile of the treated side that bonds to the resin: standard electrodeposited (ED) foil, reverse-treated foil (RTF), very-low-profile (VLP) and hyper-very-low-profile (HVLP) foil in numbered generations.
| Grade | Typical profile | Planning Rq | Where it belongs | 2026 availability |
|---|---|---|---|---|
| Standard ED (STD / HTE) | Rz ≈ 5 µm | 2.0 µm | Power and ground planes, control and low-speed layers, thick-copper layers. Best adhesion. | Readily available |
| Reverse-treated (RTF) | Rz ≈ 3 µm | 1.0 µm | Mid-loss boards and 10–25G layers. The treatment sits on the smoother drum side of the foil. | Available |
| Very low profile (VLP) | Rz ≈ 2 µm or less | 0.7 µm | 56G layers and short 112G channels. | Tight |
| HVLP, HVLP2 | Rz below 2 µm, falling with each generation | 0.45 µm | 112G signal layers on M6 and M7 laminates. | Allocated |
| HVLP3 | Rz ≤ 1.1 µm (some makers publish ≈ 0.6 µm) | 0.25 µm | Long 112G channels, 224G entry. | Allocated |
| HVLP4 (HVLP5 on roadmaps) | Rz ≈ 0.5 µm | n/a | 224G signal layers on M8–M9 laminates. | Reserved by the largest buyers |
HVLP generation numbers are foil makers' designations, not an IPC grade, and 2 makers' "HVLP3" can differ by nearly 2× in Rz. For that reason we call out high-speed foil by its maximum Rz or Rq and by the qualified foil product, not by generation number alone.
Rolled-annealed (RA) foil is a separate family: it is rolled rather than plated, very smooth and far more ductile. It is the standard choice for the flex layers of rigid-flex boards, such as the joint harnesses of humanoid robots, where the foil must survive thousands of bend cycles.
Foil can buy back more loss than a laminate upgrade
On a 20 cm, 5 mil stripline at 112G PAM4 on a Megtron 7-class laminate, our loss model puts about 8.7 of the 10.7 dB trace loss in the conductor when standard foil is used. Moving that layer to HVLP3-class foil lowers the total to about 7.8 dB, a 2.9 dB gain; moving the same channel from M7 to an M8-class laminate with the foil unchanged gains only about 0.6 dB.
| Channel | Standard ED | RTF | HVLP | HVLP3 |
|---|---|---|---|---|
| 112G on M7 | 10.7 dB | 10.5 dB | 9.3 dB | 7.8 dB |
| 112G on M8 | 10.0 dB | 9.8 dB | 8.7 dB | 7.1 dB |
| 224G on M7 | 16.4 dB | 16.2 dB | 15.3 dB | 13.4 dB |
| 224G on M8 | 15.1 dB | 14.9 dB | 14.0 dB | 12.1 dB |
This matters in 2026 because the 2 upgrades compete for the same scarce supply. When the M8 laminate is on allocation, an M7 stackup with smoother foil on the critical layers may meet the channel budget sooner. Hammerstad under-predicts loss for the roughest foils above about 20 GHz, so the real gap between standard foil and HVLP is, if anything, larger than shown. Channel sign-off still needs a field-solver or measured model.
The bonding treatment adds roughness of its own
Inner-layer copper is chemically treated before lamination so that prepreg bonds to it, and that treatment roughens the surface again. A smooth HVLP foil paired with an aggressive oxide treatment can lose much of its advantage, while a treatment that is too gentle risks delamination in reflow and thermal cycling. We confirm the fabricator's bonding process for the chosen foil and laminate and record it on the stackup, because it is qualified as a set with them.
How to call out foil on a drawing
- Per layer, not per board. Specify smooth foil only on the high-speed signal layers; planes and low-speed layers keep standard or RTF foil for adhesion and cost.
- By value. State the maximum Rz or Rq for the treated side, or name the qualified foil product, rather than writing "HVLP" alone.
- With weight. Give the foil weight (for example ½ oz or 1 oz) separately from the final plated copper thickness on outer layers.
- With the bonding treatment. Name the inner-layer bonding treatment, or leave it to the fabricator explicitly, so the loss model and the build match.
- With traceability. For aerospace and defense orders, require the foil lot and country of origin on the material declaration, alongside the laminate lot.
HVLP supply in 2026
HVLP4 foil is the tightest material in the 2026 PCB supply chain. Industry reporting puts the shortfall at about 1,500 t in 2026, widening to about 2,500 t in 2027, with 3 makers holding about 80–90% of high-end supply and overseas lead times of 6–8 months. NVIDIA has moved to secure HVLP4 foil capacity directly, upstream of the laminate makers.
New capacity is slow to arrive: specialized plating equipment is reported at about 20 lines a year worldwide, yield ramp from HVLP1 to HVLP4 at 18–24 months, and customer qualification at a further 6–12 months. At the other end of the market, Taiwan's Co-Tech announced it would stop producing standard-grade foil to concentrate on high-end grades, and much of the remaining standard-foil capacity is in mainland China, which matters for defense orders that document material origin.
Our approach follows from this. We check foil and laminate allocation with our fabricators before a stackup is frozen, propose the smoothest foil the loss budget actually needs rather than the smoothest available, and do not promise HVLP4 without written confirmation of the foil product and quantity.
Copper foil FAQ
Three questions engineers ask when a stackup review reaches the foil line.
How much does HVLP copper foil roughness matter at 224G PAM4?
At 224G PAM4 the Nyquist frequency is about 53 GHz, where the skin depth in copper is about 0.29 µm, so signal current flows in a layer thinner than the tooth profile of standard or reverse-treated foil. Surface roughness lengthens the current path and raises conductor loss, by up to about 2× for foil much rougher than the skin depth, and at these frequencies conductor loss on a 4–5 mil stripline is usually larger than the dielectric loss of an M8-grade laminate. That is why upgrading the laminate alone recovers less than the Df numbers suggest.
Our loss-budget estimator models this with the Hammerstad–Jensen roughness correction, which grows with frequency, using planning RMS roughness values from about 2.0 µm for standard ED foil down to about 0.25 µm for HVLP3-class foil (specified at Rz ≤ 1.1 µm). We specify HVLP3 or better on 224G signal layers and confirm the foil grade and inner-layer bonding treatment on the stackup drawing, because the bonding treatment adds roughness of its own.
Is HVLP3 or HVLP4 an industry standard grade?
No. HVLP generation numbers are copper foil makers' product designations, not a grade defined by IPC-4562, and published values for the same generation differ between makers: HVLP3 is quoted as Rz ≤ 1.1 µm by some sources and about 0.6 µm by others, and HVLP4 at about 0.5 µm. Two foils sold under the same generation name can therefore behave differently on a 112G or 224G channel.
On a stackup drawing we specify high-speed foil by its maximum treated-side Rz or Rq, or by the named foil product qualified with the laminate, and we record the inner-layer bonding treatment, which adds roughness of its own. The foil product and lot then appear on the material declaration shipped with the boards.
Does the copper foil's country of origin matter for defense PCBs?
It can. 10 U.S.C. 4873 and the July 2026 advance notice of proposed rulemaking focus on where the bare board is fabricated, but prime contractors increasingly ask for traceability of the laminate and copper foil behind the board, and much of the world's standard-grade foil capacity is in mainland China. High-end HVLP foil comes mainly from Japanese, Taiwanese and Luxembourg producers.
For aerospace and defense orders we record the foil product, lot and country of origin on the material declaration alongside the laminate lot, so the origin package covers the board, the laminate and the foil. Whether a specific program requires material-level origin is set by the contract; confirm it with your contracting officer.
Trading off foil and laminate on your channel?
Send the lane rate, the longest channel and your laminate. We return a stackup with foil called out layer by layer and a loss estimate for each option.
References
- E. O. Hammerstad and Ø. Jensen, "Accurate models for microstrip computer-aided design", IEEE MTT-S 1980; IPC technical paper "Effect of Conductor Surface Roughness upon Measured Loss and Extracted Values" (foil Rq values).
- Eagle Driver, "HVLP3–HVLP4 application experience" (STD, RTF and HVLP profile); ship.ie glossary, "HVLP" (HVLP below 2 µm Rz; HVLP3 ≤ 1.1 µm Rz); PCBSync, IPC-4562 guide (foil types and profiles).
- DIGITIMES, "Taiwan's Co-tech to halt standard copper foil, double down on AI" (Aug 2025) and "Nvidia takes PCB material competition upstream as HVLP4 copper foil tightens" (Jun 2026).
- PCBA-HYH, "AI servers are stuck on copper foil: HVLP supply gap hits 1,500 tons" (Jul 2026): shortfall, supplier share, lead time, equipment and qualification timelines.
- Panasonic Megtron 7 (N) and Megtron 8 (N) datasheets: Dk and Df used in the example.
Last reviewed . Values are typical published figures for stackup planning; confirm foil product data with the fabricator before release.