Seven checks and the method behind each
Seven checks cover most AI board drawings: insertion loss, impedance, plated-hole reliability, thermal shock, reflow survival, CAF resistance and warpage. Each has a published method, so a limit on the drawing can be inspected and reported.
| What is proved | Method | How it works | Put on the drawing |
|---|---|---|---|
| Insertion loss | IPC-TM-650 2.5.5.12A (VNA, SPP, SET2DIL, Delta-L); 2.5.5.14 (frequency domain, incorporates Delta-L) | Coupons on the production panel; Delta-L subtracts two line lengths to remove probe and via effects | Method, coupon design, frequencies, dB/inch limit |
| Differential and single-ended impedance | IPC-TM-650 2.5.5.7A, TDR | Time-domain reflectometry on impedance coupons | Target Ω and tolerance per net class (±10% standard; ±7% or ±5% tighter) |
| Plated-hole and via reliability | IPC-TM-650 2.6.26A, IST | DC current heats the coupon's interconnects in fast thermal cycles until resistance rises | Cycle count, temperature and failure criterion |
| Thermal shock | IPC-TM-650 2.6.7.2 | Temperature cycling of coupons with continuity monitoring; part of IPC-6012 Class 3 qualification | Required for Class 3 / 3A |
| Survival of assembly reflow | IPC-TM-650 2.6.27B | Convection reflow simulation at lead-free profiles, then inspection of the coupons | Number of reflow passes (assembly plus rework) |
| CAF resistance | IPC-TM-650 2.6.25C; IPC-9691B user guide | Bias and humidity on a hole-to-hole pattern, watching insulation resistance | Named CAF-resistant laminate and test data at a comparable hole pitch |
| Bow, twist and package-site flatness | IPC-TM-650 2.4.22C; IPC-9641; JEDEC JESD22-B112 / JEITA ED-7306 for the package | Board bow and twist at room temperature; flatness and package warpage at reflow temperature | Bow and twist % and a local flatness limit under large BGAs |
Insertion loss: Delta-L or SET2DIL
Delta-L and SET2DIL answer different questions. Delta-L measures two line lengths and subtracts them, so probe and via effects cancel and the result is loss per inch at chosen frequencies. That is the number to compare with a channel budget and with the loss-per-inch table. SET2DIL converts a single-ended TDR measurement into differential insertion loss. It is quick enough to screen every production lot against a limit, but it is less suited to characterizing a new material. Many programs qualify a stackup with Delta-L and then screen lots with SET2DIL. Either way, the coupon must use the same laminate, glass style, foil and trace geometry as the product's high-speed layers. Otherwise it proves a different board.
Impedance tolerance
±10% is the standard controlled-impedance tolerance. ±7% or ±5% is offered by many fabricators at extra cost and with coupons on every panel. A tighter tolerance depends on three things: controlled dielectric thickness, etch compensation on trace width, and a Dk measured for the exact construction rather than taken from a datasheet. IPC-2141A is the design guide, and the measured coupon, not the design value, is what passes or fails.
Plated-hole reliability on thick boards
On a 4–6 mm, 30–40 layer board the main reliability risk is z-axis expansion stretching the copper barrel of each plated hole during reflow and power cycling. IST (IPC-TM-650 2.6.26A) finds these weaknesses in hours rather than weeks, so it is the usual qualification test for thick boards. Reflow simulation (2.6.27B) confirms the board survives the number of lead-free passes that assembly and rework will apply. Aspect ratio feeds directly into this risk. Plan through-holes at about 10:1 and treat 12:1 to 14:1 as advanced capability; the stackup calculator checks it against your smallest drilled hole.
IPC Class 2 or Class 3
Commercial server and AI boards are commonly bought to IPC-6012 Class 2, "dedicated service electronic products", with a customer specification that tightens selected attributes. Class 3, "high performance/harsh environment electronic products" in IPC-6011A, adds inspection and microsection requirements. It is specified when continued performance on demand is required, as in aerospace and defense. The class on the drawing decides how the boards are inspected and what the inspection records say.
Reports to ask for
Six reports belong with an AI accelerator baseboard shipment:
- a certificate of conformance naming the fabrication site;
- electrical test results;
- the impedance (TDR) report;
- microsection reports to the drawing's IPC class;
- the insertion loss coupon report, where the drawing sets a limit;
- a material declaration naming laminate, glass style and copper foil.
Every Tecsply PCB order ships with the signed stackup, the material declaration, inspection records to the specified IPC-6012 class and country-of-origin records for the board, the laminate and the foil. Further reports are added when the drawing or purchase order lists them.
Testing FAQ
Six questions from AI board test and quality reviews; the full list is on the FAQ page.
How is PCB insertion loss verified in production: Delta-L, SET2DIL or something else?
Production insertion loss is verified on test coupons built on the same panel as the boards, not on the boards themselves. Two IPC method documents cover it. IPC-TM-650 2.5.5.12A covers VNA, SPP, SET2DIL and Delta-L. IPC-TM-650 2.5.5.14 (2021) is a frequency-domain method that incorporates Intel's Delta-L. SET2DIL converts a single-ended TDR measurement into differential insertion loss, which makes it fast enough to screen production lots. Delta-L measures two line lengths and subtracts them to remove probe and via effects, then reports loss per inch at set frequencies. Agree the method, the coupon design, the frequency points and the pass limit on the fabrication drawing; without them there is no loss requirement to inspect against.
What impedance tolerance can be held on 85, 90 and 100 ohm differential pairs?
±10% is the standard controlled-impedance tolerance. Many fabricators offer ±7% or ±5% as a tighter option, at extra cost and with test coupons on every panel. Holding a tighter tolerance needs controlled dielectric thickness (resin content and press), trace-width etch compensation, and a known Dk for the exact construction. The 85 Ω pairs used for PCIe and the 90 Ω and 100 Ω pairs used for Ethernet SerDes are specified the same way. The tolerance applies to the measured coupon, tested by TDR per IPC-TM-650 2.5.5.7A, with IPC-2141A as the design guide. Ask for the impedance test report to ship with the boards.
Which reliability tests prove a thick high-layer-count PCB?
Use three tests together:
- Interconnect stress testing (IST, IPC-TM-650 2.6.26A, "DC Current Induced Thermal Cycling Test") heats coupons with DC current. It finds plated-hole and via weaknesses in hours rather than weeks, and it is the usual test for thick boards.
- Thermal shock per IPC-TM-650 2.6.7.2 is part of IPC-6012 Class 3 qualification.
- Convection reflow simulation per IPC-TM-650 2.6.27B shows whether the board survives the number of lead-free reflow passes that assembly and rework will apply.
Add CAF testing per IPC-TM-650 2.6.25C where hole spacing is tight. On a 4–6 mm board the main risk is z-axis expansion stretching the copper barrel, so these tests matter more than on a thin board.
Is CAF a risk on high-layer-count AI server PCBs, and how is it tested?
Yes. Conductive anodic filament (CAF) growth becomes more likely as the spacing between plated holes shrinks and as a board spends years powered in a warm, humid data hall. Dense via fields under large AI packages are exactly that case. Specify a CAF-resistant laminate by name and ask for CAF test data per IPC-TM-650 2.6.25C, with IPC-9691B as the user guide for the test. CAF resistance depends on the resin system, the glass finish and the fabricator's drilling and desmear quality together, so the test data should come from the same laminate and a comparable hole pitch.
Should AI server PCBs be built to IPC-6012 Class 2 or Class 3?
Commercial server and AI boards are commonly bought to IPC-6012 Class 2, "dedicated service electronic products", plus a customer specification that tightens selected attributes such as plating thickness, annular ring or microsection sampling. Class 3, "high performance/harsh environment electronic products" in IPC-6011A ("high reliability" in earlier revisions), is specified when the program needs continued performance on demand, as in aerospace, defense and some infrastructure equipment. Class 3 adds inspection and microsection requirements and usually cost. The class and any added requirements belong on the fabrication drawing, because the inspection records shipped with the boards are written to that class.
Which test reports should ship with an AI accelerator baseboard PCB?
At minimum:
- a certificate of conformance naming the fabrication site;
- the electrical test result for every board;
- the impedance test report from TDR coupons;
- microsection reports to the IPC-6012 class on the drawing;
- the insertion loss coupon report, where the drawing sets a loss limit;
- a material declaration naming the laminate, glass style and copper foil.
Programs with origin rules add country-of-origin records for the board, the laminate and the foil. Every Tecsply PCB order ships with the signed stackup, the material declaration, inspection records to the specified IPC-6012 class and country-of-origin records. Additional reports are listed on the drawing or in the purchase order.
Send the drawing with its test requirements
Share the stackup, the net classes with impedance targets, any loss limit and the IPC class; we return a stackup review with named materials and the test coupons it needs.
References
- IPC-TM-650 test methods (electronics.org/test-methods): 2.4.22C Bow and Twist; 2.5.5.7A Characteristic Impedance Lines on Printed Boards by TDR; 2.5.5.12A Test Methods to Determine the Amount of Signal Loss on Printed Boards; 2.5.5.14 Measuring High Frequency Signal Loss and Propagation on Printed Boards with Frequency Domain Methods (2021); 2.6.7.2 Thermal Shock, Thermal Cycle and Continuity; 2.6.25C Conductive Anodic Filament (CAF) Resistance Test: X-Y Axis; 2.6.26A DC Current Induced Thermal Cycling Test; 2.6.27B Thermal Stress, Convection Reflow Assembly Simulation.
- IPC-6012E, Qualification and Performance Specification for Rigid Printed Boards: 1.4.1 Back-Drilling, 1.4.2 Stub, 3.3.9 Back-Drilled Holes, 3.4.3 Bow and Twist. IPC-6011A performance class definitions.
- IPC-2141A, Design Guide for High-Speed Controlled Impedance Circuit Boards; IPC-9691B, CAF test user guide; IPC-9641, High Temperature Printed Board Flatness Guideline.
- JEDEC JESD22-B112, High-Temperature Package Warpage Measurement Methodology; JEITA ED-7306, package warpage at elevated temperature.
- Keysight, application material on IPC-TM-650 2.5.5.14 and Intel's Delta-L method.