Three AI board families, three different limits
Accelerator baseboards, cluster switches and rack power shelves use 16–32, 18–28 and 6–14 layers respectively, and each is limited by a different physical effect. We quote them as three separate material problems.
| Board | Typical layers · thickness | First limit | Material response |
|---|---|---|---|
| AI accelerator / GPU baseboard | 16–24 · 2.4–3.6 mm 20–32 · 3.2–5.0 mm (package > 60 mm) | Channel loss and BGA warpage | Very-low or ultra-low-loss CCL on signal layers; T-glass outer cores under the package |
| Cluster switch / NIC (800G–1.6T) | 18–28 · 3.0–4.5 mm | Channel loss and skew across long SerDes routes | Ultra-low-loss CCL, spread glass, HVLP3 foil on 224G layers |
| Rack power shelf / busbar board | 6–14 · 3.0–6.0 mm | z-axis expansion on PTH barrels, current density | 7628 multi-ply cores, 2–6 oz copper, wrap plating, high-Tg low z-CTE laminate; T-glass above 3.0 mm for flatness |
CCL loss grades used on AI boards
Three of the six laminate loss grades Tecsply specifies, M6 (Df 0.003–0.005 at 10–14 GHz), M7 (0.002–0.003) and M8 (below 0.002), cover almost every signal layer on an AI board. The rows below are taken from our full CCL table; the plane and power layers inside the same board can use a lower grade.
| Loss grade | Df @ 10 GHz | Dk @ 10 GHz | Representative CCL | Where we specify it |
|---|---|---|---|---|
| Low loss (M6 grade) | 0.003–0.005 | 3.3–3.7 | Megtron 6 class (R-5775(N): 3.34 / 0.0037 @ 13 GHz) | 56G PAM4; power/ground planes inside AI boards where signal layers use a lower-loss grade |
| Very low loss (M7 grade) | 0.002–0.003 | 2.9–3.4 | Megtron 7, Tachyon 100G, EM-890K class | 112G PAM4; PCIe Gen5/Gen6; 112G-generation accelerator and switch boards |
| Ultra low loss (M8 grade) | < 0.002 | 2.9–3.2 | Megtron 8, Astra MT77, EM-892K class | 224G PAM4; 224G-generation accelerator baseboards and 1.6T switches |
Dielectric loss scales roughly with Df × √Dk × frequency × trace length. On a 20 cm 112G channel, moving from Megtron 6 to Megtron 7 class recovers about 1.2 dB of dielectric loss, and at that point conductor loss from the copper foil is the larger term, so we quote the signal layers and the plane layers as two separate material decisions.
Material mapping for 56G, 112G and 224G PAM4
A PAM4 lane's Nyquist frequency is half its baud rate, so a 106.25 Gb/s "112G" lane is evaluated at 26.56 GHz and a 212.5 Gb/s "224G" lane at 53.13 GHz, and each doubling of data rate moves the board up one laminate loss grade. The table summarizes the default construction we open a 56G, 112G or 224G stackup review with.
| Lane | Nyquist | CCL grade | Signal-layer glass | Thin-dielectric style | Copper foil |
|---|---|---|---|---|---|
| 56G PAM4 | 13.3 GHz | M6 (Megtron 6 class) | NE-glass / L-glass | 1078 / 1080 | Per channel length |
| 112G PAM4 | 26.6 GHz | M7 (Megtron 7 / Tachyon 100G / EM-890K class) | NE-glass / L-glass, spread | 1067 / 1078 | Per channel length |
| 224G PAM4 | 53.1 GHz | M8 (Megtron 8 / EM-892K / Astra MT77 class); PTFE on channels over 25 cm | NE-glass / L-glass, spread | 1027 / 1037 | HVLP3 or better |
Our loss budget estimator runs the same first-order model we use in the first call: dielectric loss from Df and Dk, conductor loss from trace width with a frequency-dependent copper-roughness correction, compared against an IEEE channel budget. Use it to see which grade a given channel length needs before you commit to a laminate.
Insertion loss per inch at 112G and 224G
On a 5 mil stripline with HVLP3-class foil, M6, M7 and M8 grade laminates lose about 1.1, 1.0 and 0.9 dB per inch at the 26.56 GHz Nyquist frequency of 112G PAM4, and about 2.0, 1.7 and 1.5 dB per inch at the 53.13 GHz Nyquist frequency of 224G PAM4. At this trace width conductor loss is larger than dielectric loss, which is why one foil grade can matter more than one laminate grade.
| Laminate class | 112G, VLP foil | 112G, HVLP3 foil | 224G, VLP foil | 224G, HVLP3 foil |
|---|---|---|---|---|
| M6 (Megtron 6(N)) | 1.44 dB/in | 1.14 dB/in | 2.34 dB/in | 2.02 dB/in |
| M7 (Megtron 7(N)) | 1.29 dB/in | 0.99 dB/in | 2.03 dB/in | 1.71 dB/in |
| M8 (Megtron 8(N)) | 1.20 dB/in | 0.90 dB/in | 1.86 dB/in | 1.54 dB/in |
Read the table against the IEEE die-to-die budgets of 28 dB at 26.56 GHz and 40 dB at 53.13 GHz, after connector, via and package losses are taken out. Datasheet Df usually rises above 14 GHz, so the 224G columns are the more optimistic ones; see how to get Dk/Df at 28 to 56 GHz. Surface finish does not change these stripline values; it matters only on outer-layer microstrip.
Mixed-glass stackups: NE-glass for the lanes, T-glass for the package
An AI accelerator board with packages over 80 mm on a side needs low-Dk glass on its signal layers and low-CTE glass under its BGA field, because a board that bows by even 0.2 mm across the package opens solder joints during reflow. The lanes want NE-glass or L-glass for loss and skew. The package wants T-glass, whose coefficient of thermal expansion is about 2.8 ppm/°C against 5.6 ppm/°C for E-glass, and whose tensile modulus is about 15% higher (86 vs 75 GPa).
The practical answer is a mixed stackup: low-Dk cloth on the signal-pair layers, low-CTE cloth in the outer cores under the package, and a fabricator who can laminate both in one press cycle without registration drift. Two cloths with different expansion and resin uptake behave differently in the press, so the fabricator has to qualify the combination, not each cloth alone. We check that qualification before we place the order, and we record which layer carries which cloth on the stackup drawing.
T-glass has its own supply constraint. Production-grade T-glass cloth is dominated by a single Japanese supplier, with Taiwanese producers recently qualified, so lead time is checked before a mixed-glass stackup is frozen. See the T-glass guide for the full glass-type comparison.
Fiber-weave skew above 25 Gbps
Fiber-weave skew closes the eye on differential pairs at 56G and above, and Tecsply specifies spread glass by default on any board above 25 Gbps to limit it. A trace running over a glass yarn sees a higher local Dk than one running over resin between yarns; when the two legs of a pair see different Dk, they arrive at different times.
Three measures reduce it, and they stack. Spread-glass styles (1067, 1078, 3313) flatten the yarn so the Dk under a trace is more uniform. Low-Dk glass narrows the gap between glass Dk and resin Dk, so even an uneven weave matters less. Rotated-panel or zig-zag routing adds a further margin by making each leg cross the weave at an angle. On 224G layers we typically combine all three with the thinnest spread styles, 1027 and 1037.
Copper foil roughness at 112G and 224G
At 224G PAM4 the skin depth in copper at the 53 GHz Nyquist frequency is about 0.29 µm, so foil roughness drives conductor loss as much as the laminate's Df does. We specify HVLP3 or better on 224G signal layers and treat foil grade as a line item on the stackup, not a fabricator default. The FAQ below covers how we model it.
Rack power and busbar boards
AI rack power shelves typically run 6 to 14 layers at 3.0 to 6.0 mm total thickness with 2–6 oz copper, which makes z-axis expansion on plated through-hole barrels the main reliability risk. We build them on 7628 multi-ply cores, specify wrap plating on PTH and a high-Tg laminate with low z-axis expansion, and consider T-glass once total thickness passes 3.0 mm to keep the board flat; T-glass lowers in-plane expansion, not z-axis expansion. The loss grade on these boards follows any adjacent signal layer rather than the power layers themselves. The shelf enclosure, copper busbars and cold plates around the board come from our Thermal, Enclosures & Aerospace Machining division as a separate quote.
800 V DC racks change the board's first rule from current to spacing. NVIDIA announced an 800 V HVDC architecture for AI data centers in May 2025, with production planned alongside its Kyber rack systems in 2027. At 800 V the current for the same power is far lower, so less copper is needed, but conductor spacing, creepage and insulation then govern the layout: spacing per IPC-2221 and the end product's safety standard, current capacity per IPC-2152.
Testing and qualification
Loss, impedance and reliability on an AI board are proved on coupons built on the same panel. Insertion loss is measured by Delta-L or SET2DIL (IPC-TM-650 2.5.5.12A, 2.5.5.14), impedance by TDR (2.5.5.7A), and plated-hole reliability by IST (2.6.26A) and reflow simulation (2.6.27B). Which tests apply, and to what limits, is written on the fabrication drawing. The methods, the reports that ship with the boards and the choice between IPC Class 2 and Class 3 are covered in AI server PCB testing and qualification.
AI compute FAQ
These questions come up in almost every AI board stackup review; the full list is on the FAQ page.
Which CCL loss grade does a 112G or 224G PAM4 board need?
112G PAM4 channels (Nyquist 26.56 GHz) are typically built on M7-grade very-low-loss CCL with Df around 0.002–0.003 at 10–14 GHz (Megtron 7, Tachyon 100G, EM-890K class). 224G PAM4 (Nyquist 53.13 GHz) moves to M8-grade ultra-low-loss laminates below 0.002 (Megtron 8, EM-892K, Astra MT77 class) and, on the longest channels, PTFE-based materials such as RO3003. Plane layers inside the same board can use a lower grade.
What is fiber-weave skew and how does glass style affect it?
A trace running over a glass yarn sees a higher local Dk than one running over resin between yarns. On a differential pair this shows up as skew, which closes the eye at 56G and above. Spread-glass styles (1067, 1078, 3313) flatten the yarn so the Dk is more uniform; low-Dk glass narrows the gap between glass and resin Dk; rotated-panel or zig-zag routing adds a further margin. We specify spread glass by default on any board above 25 Gbps.
Is T-glass the same as low-Dk glass?
No. T-glass is defined by low CTE (about 2.8 ppm/°C) and high modulus (about 86 GPa), not by its dielectric properties: its Dk is about 5.4 and its Df about 0.0043 at 1 GHz, higher loss than E-glass (Nittobo published values). Low-Dk glass such as NE-glass has a Dk of about 4.8 at 1 GHz against 6.8 for E-glass, with a CTE of about 3.3 ppm/°C but a lower modulus (about 64 GPa). Some suppliers offer low-CTE, low-Dk hybrid cloths, and current AI boards often combine both types in one stackup.
How much does HVLP copper foil roughness matter at 224G PAM4?
At 224G PAM4 the Nyquist frequency is about 53 GHz, where the skin depth in copper is about 0.29 µm, so signal current flows in a layer thinner than the tooth profile of standard or reverse-treated foil. Surface roughness lengthens the current path and raises conductor loss, by up to about 2× for foil much rougher than the skin depth, and at these frequencies conductor loss on a 4–5 mil stripline is usually larger than the dielectric loss of an M8-grade laminate. That is why upgrading the laminate alone recovers less than the Df numbers suggest.
Our loss-budget estimator models this with the Hammerstad–Jensen roughness correction, which grows with frequency, using planning RMS roughness values from about 2.0 µm for standard ED foil down to about 0.25 µm for HVLP3-class foil (specified at Rz ≤ 1.1 µm). We specify HVLP3 or better on 224G signal layers and confirm the foil grade and inner-layer bonding treatment on the stackup drawing, because the bonding treatment adds roughness of its own.
Which PCB laminate do PCIe Gen6 and PCIe Gen7 need?
PCIe Gen6 runs 64 GT/s PAM4 with a Nyquist frequency of about 16 GHz, the same as Gen5, and its laminate grade follows channel length: M6 grade covers short channels and M7 grade the long channels of a server board. PCIe Gen7, released by PCI-SIG on June 11, 2025, runs 128 GT/s PAM4 at about 32 GHz Nyquist, closer to 112G PAM4 (26.56 GHz) than to Gen6. We therefore start Gen7 stackup reviews at M7 grade with low-roughness foil and spread glass, and check long channels in the loss budget estimator before a grade is fixed.
How does surface finish (ENIG, immersion silver, ENEPIG, OSP) affect insertion loss at 112G and 224G?
Surface finish only affects outer-layer microstrip, and there ENIG adds the most loss: its electroless nickel is ferromagnetic, so at multi-GHz frequencies the current that skin effect pushes to the surface meets higher resistance than in copper. Immersion silver (IPC-4553A) and OSP leave the copper close to bare and give the lowest loss. ENEPIG (IPC-4556) still has a nickel layer, so it behaves more like ENIG (IPC-4552B) than like silver. Inner-layer striplines, which carry most 112G and 224G channels on AI boards, are not affected by the finish at all. The practical rule is to route long high-speed channels as striplines and keep microstrip breakouts short. Where a long microstrip run cannot be avoided, choose immersion silver or OSP over ENIG. The finish must also suit assembly and shelf life, so it is agreed with the EMS.
Can I use Megtron 8 on the signal layers and a cheaper laminate on the power planes of the same board?
Yes. Putting the ultra-low-loss laminate only on the high-speed signal layers and a lower grade on the plane and power layers is a common way to cut material cost on a 20–30 layer AI board. The condition is that the fabricator has qualified that exact combination. Different resin systems differ in cure temperature, resin flow and z-axis expansion, so a mixed press can warp or delaminate if the pair has never been run together. Most hybrid builds stay within one supplier's family, for example an M8-grade signal core with an M6-grade plane core from the same maker, and the stackup drawing names the laminate for every layer.
What aspect ratio and minimum drill size are realistic on a 5 to 6 mm thick, 30 to 40 layer PCB?
Plan plated through-holes at about 10:1 (board thickness to drilled hole diameter) for standard plating. Treat 12:1 to 14:1 as advanced capability to confirm with the fabricator, and above that use back-drilled, blind or sequentially laminated structures. On a 5.0 mm board, 10:1 means a 0.50 mm drilled hole, and even 14:1 needs about 0.36 mm. That is why thick 30–40 layer AI boards often combine larger through-holes for press-fit and power with blind or buried vias for fine-pitch breakout (IPC-2226A covers HDI structures). Aspect ratio is calculated on the drilled hole, not the finished hole. Our stackup calculator checks aspect ratio against your smallest drilled hole, and the readiness pre-check flags anything above 10:1 for review and above 12:1 as a likely engineering query.
What back-drill stub length should I specify for 112G and 224G channels?
Put a maximum remaining stub length and the must-not-cut layer on the fabrication drawing. IPC-6012E defines back-drilled holes and stubs (sections 1.4.1, 1.4.2 and 3.3.9) but leaves the stub limit to the procurement documents. The limit follows from the stub's quarter-wave resonance: a 30 mil (0.76 mm) stub in a Dk 3.2 laminate resonates near 55 GHz, right at the 53 GHz Nyquist frequency of 224G PAM4, so 224G channels need stubs well below that. Published fabricator capability varies. One large North American fabricator quotes a nominal stub of about 7 ± 5 mil from the must-not-cut layer in its back-drilling bulletin, and advanced shops report about 4 ± 2 mil. The number you can hold is therefore a fabricator capability to confirm in the stackup review, not a standard value.
What PCB warpage limit should I specify under an 80 mm or larger BGA package?
Specify a local flatness limit over the package site at reflow temperature, agreed with the EMS, in addition to the board's overall bow and twist. The IPC-6012E default of 0.75% for boards with surface-mount parts (section 3.4.3, measured per IPC-TM-650 2.4.22C) allows about 0.6 mm of bow across an 80 mm span, while a board that bows by even 0.2 mm across a package of that size can open solder joints during reflow. Package warpage at temperature is measured per JEDEC JESD22-B112 or JEITA ED-7306, and IPC-9641 gives guidance on board flatness at high temperature. On the material side, low-CTE T-glass in the outer cores under the package is the main lever; see the T-glass guide.
Check a channel, then send us the board
Run your longest lane through the loss estimator, then send the data rate, package size and layer count for a stackup review with named CCL and glass constructions.
References
- Panasonic MEGTRON 6(N) / 7(N) / 8(N), Isola Tachyon 100G / Astra MT77 and EMC EM-890K / EM-892K supplier datasheets: Dk/Df at 10–14 GHz.
- IEEE 802.3ck and 802.3dj: 100GBASE-KR1 and 200GBASE-KR1 channel insertion-loss limits.
- Nittobo Electronic Materials: glass cloth types (E, NE, T) and style thickness tables.
- E. Bogatin, Signal and Power Integrity – Simplified: first-order dielectric and conductor loss approximations.
- NCAB Group PCB Supply Chain Outlook, September 2026; AtlasPCB material cost and lead-time reporting, July–August 2026.
- IPC-TM-650 test methods 2.5.5.7A, 2.5.5.12A, 2.5.5.14, 2.6.26A and 2.6.27B (electronics.org/test-methods); IPC-6012E sections 1.4.1, 1.4.2, 3.3.9 and 3.4.3; IPC-2152; IPC-2221.
- NVIDIA Technical Blog, "NVIDIA 800 V HVDC Architecture Will Power the Next Generation of AI Factories", May 2025.
- PCI-SIG, PCI Express 7.0 specification release, June 11, 2025 (128 GT/s PAM4).