Multilayer PCB FAQ

T-glass is a high-silica, high-modulus glass fiber woven into glass cloth for PCB laminates and IC substrates. Its defining properties are a coefficient of thermal expansion of about 2.8 ppm/°C, half that of standard E-glass at 5.6 ppm/°C, and a tensile modulus of about 86 GPa against 75 GPa for E-glass (Nittobo published values). In a laminate, the lower expansion and higher stiffness reduce in-plane expansion and warpage, which is why T-glass is used in the cores under packages larger than 60 mm, in substrate-like PCBs and in IC substrate cores. It is not a low-loss glass: its Df at 1 GHz (0.0043) is higher than E-glass (0.0035), and expansion through the board's thickness is set mainly by the resin system, not by the glass. Production-grade T-glass cloth is dominated by a single Japanese supplier, so lead time is checked before a stackup is frozen. See the T-glass guide.

E-glass is the standard reinforcement in FR-4, with a fiber Dk of about 6.8 at 1 GHz and a CTE of about 5.6 ppm/°C. T-glass is a high-silica, high-modulus glass with a CTE of about 2.8 ppm/°C, half that of E-glass, and a tensile modulus of about 86 GPa against 75 GPa for E-glass (Nittobo published values). Choose T-glass when warpage and dimensional stability limit the design, such as boards under packages larger than 60 mm or thick boards that must stay flat. T-glass lowers the laminate's in-plane (X,Y) expansion; expansion through the board's thickness, which strains plated through-holes, is set mainly by the resin system and is specified through the laminate's z-axis CTE. For the lowest dielectric loss, NE-glass is usually the better reinforcement.

No. T-glass is defined by low CTE (about 2.8 ppm/°C) and high modulus (about 86 GPa), not by its dielectric properties: its Dk is about 5.4 and its Df about 0.0043 at 1 GHz, higher loss than E-glass (Nittobo published values). Low-Dk glass such as NE-glass has a Dk of about 4.8 at 1 GHz against 6.8 for E-glass, with a CTE of about 3.3 ppm/°C but a lower modulus (about 64 GPa). Some suppliers offer low-CTE, low-Dk hybrid cloths, and current AI boards often combine both types in one stackup.

A copper clad laminate core is a cured sheet of glass cloth and resin with copper foil bonded to one or both sides; prepreg is the same glass-and-resin system left uncured, so it flows and bonds the cores together during lamination. In a typical foil-construction multilayer, the outer layers are copper foil pressed onto prepreg, and the inner layers are etched cores separated by prepreg. The resin system sets Dk, Df, Tg and z-axis expansion for both.

Signal pairs use thin cores and prepreg of 0.04–0.13 mm built from fine, spread-glass styles (1027, 1037, 1067, 1078) so that trace width and dielectric spacing hit the impedance target. Power planes use standard or thick dielectrics of 0.13–1.6 mm with 2116 or 7628 glass and 2 oz or heavier copper. Backplanes stack multiple 7628 plies and can exceed 5 mm total.

112G PAM4 channels (Nyquist 26.56 GHz) are typically built on M7-grade very-low-loss CCL with Df around 0.002–0.003 at 10–14 GHz (Megtron 7, Tachyon 100G, EM-890K class). 224G PAM4 (Nyquist 53.13 GHz) moves to M8-grade ultra-low-loss laminates below 0.002 (Megtron 8, EM-892K, Astra MT77 class) and, on the longest channels, PTFE-based materials such as RO3003. Plane layers inside the same board can use a lower grade.

A trace running over a glass yarn sees a higher local Dk than one running over resin between yarns. On a differential pair this shows up as skew, which closes the eye at 56G and above. Spread-glass styles (1067, 1078, 3313) flatten the yarn so the Dk is more uniform; low-Dk glass narrows the gap between glass and resin Dk; rotated-panel or zig-zag routing adds a further margin. We specify spread glass by default on any board above 25 Gbps.

At 224G PAM4 the Nyquist frequency is about 53 GHz, where the skin depth in copper is about 0.29 µm, so signal current flows in a layer thinner than the tooth profile of standard or reverse-treated foil. Surface roughness lengthens the current path and raises conductor loss, by up to about 2× for foil much rougher than the skin depth, and at these frequencies conductor loss on a 4–5 mil stripline is usually larger than the dielectric loss of an M8-grade laminate. That is why upgrading the laminate alone recovers less than the Df numbers suggest.

Our loss-budget estimator models this with the Hammerstad–Jensen roughness correction, which grows with frequency, using planning RMS roughness values from about 2.0 µm for standard ED foil down to about 0.25 µm for HVLP3-class foil (specified at Rz ≤ 1.1 µm). We specify HVLP3 or better on 224G signal layers and confirm the foil grade and inner-layer bonding treatment on the stackup drawing, because the bonding treatment adds roughness of its own.

No. HVLP generation numbers are copper foil makers' product designations, not a grade defined by IPC-4562, and published values for the same generation differ between makers: HVLP3 is quoted as Rz ≤ 1.1 µm by some sources and about 0.6 µm by others, and HVLP4 at about 0.5 µm. Two foils sold under the same generation name can therefore behave differently on a 112G or 224G channel.

On a stackup drawing we specify high-speed foil by its maximum treated-side Rz or Rq, or by the named foil product qualified with the laminate, and we record the inner-layer bonding treatment, which adds roughness of its own. The foil product and lot then appear on the material declaration shipped with the boards.

On a 5 mil stripline with HVLP3-class copper foil, a first-order model gives about 1.1, 1.0 and 0.9 dB per inch for Megtron 6(N), 7(N) and 8(N) class laminates at 26.56 GHz, the Nyquist frequency of 112G PAM4, and about 2.0, 1.7 and 1.5 dB per inch at 53.13 GHz, the Nyquist frequency of 224G PAM4. With rougher VLP-class foil the same lines lose about 1.4, 1.3 and 1.2 dB per inch at 26.56 GHz. At these trace widths conductor loss is the larger term, so the foil and the trace width move the result as much as the laminate grade does. The model holds the supplier's 13–14 GHz datasheet Dk and Df constant with frequency, which can understate loss at 53 GHz; treat the figures as planning values within about ±20% and confirm with a field solver or measured coupons. The same model runs in our loss budget estimator.

Ask the laminate supplier for its Dk/Df-versus-frequency data for the exact construction (glass style and resin content), and simulate with a frequency-dependent model rather than one 10 GHz value. Datasheets usually quote Dk and Df at one to three frequencies between 1 and 14 GHz on one specific construction. For most low-loss resin systems Df keeps rising slowly and Dk falls slightly above that range, so a single 10 GHz value can understate loss at the 53 GHz Nyquist frequency of 224G PAM4. Two common lab methods are the split-cylinder resonator, IPC-TM-650 2.5.5.13, used well above 10 GHz, and the X-band stripline test, IPC-TM-650 2.5.5.5C. Many teams also extract an effective Dk and Df from insertion loss measured on test coupons (IPC-TM-650 2.5.5.12A or 2.5.5.14), which folds in copper roughness. We name the construction layer by layer on the stackup so the values used in simulation match the board that is built.

PCIe Gen6 runs 64 GT/s PAM4 with a Nyquist frequency of about 16 GHz, the same as Gen5, and its laminate grade follows channel length: M6 grade covers short channels and M7 grade the long channels of a server board. PCIe Gen7, released by PCI-SIG on June 11, 2025, runs 128 GT/s PAM4 at about 32 GHz Nyquist, closer to 112G PAM4 (26.56 GHz) than to Gen6. We therefore start Gen7 stackup reviews at M7 grade with low-roughness foil and spread glass, and check long channels in the loss budget estimator before a grade is fixed.

Surface finish only affects outer-layer microstrip, and there ENIG adds the most loss: its electroless nickel is ferromagnetic, so at multi-GHz frequencies the current that skin effect pushes to the surface meets higher resistance than in copper. Immersion silver (IPC-4553A) and OSP leave the copper close to bare and give the lowest loss. ENEPIG (IPC-4556) still has a nickel layer, so it behaves more like ENIG (IPC-4552B) than like silver. Inner-layer striplines, which carry most 112G and 224G channels on AI boards, are not affected by the finish at all. The practical rule is to route long high-speed channels as striplines and keep microstrip breakouts short. Where a long microstrip run cannot be avoided, choose immersion silver or OSP over ENIG. The finish must also suit assembly and shelf life, so it is agreed with the EMS.

Yes. Putting the ultra-low-loss laminate only on the high-speed signal layers and a lower grade on the plane and power layers is a common way to cut material cost on a 20–30 layer AI board. The condition is that the fabricator has qualified that exact combination. Different resin systems differ in cure temperature, resin flow and z-axis expansion, so a mixed press can warp or delaminate if the pair has never been run together. Most hybrid builds stay within one supplier's family, for example an M8-grade signal core with an M6-grade plane core from the same maker, and the stackup drawing names the laminate for every layer.

Plan plated through-holes at about 10:1 (board thickness to drilled hole diameter) for standard plating. Treat 12:1 to 14:1 as advanced capability to confirm with the fabricator, and above that use back-drilled, blind or sequentially laminated structures. On a 5.0 mm board, 10:1 means a 0.50 mm drilled hole, and even 14:1 needs about 0.36 mm. That is why thick 30–40 layer AI boards often combine larger through-holes for press-fit and power with blind or buried vias for fine-pitch breakout (IPC-2226A covers HDI structures). Aspect ratio is calculated on the drilled hole, not the finished hole. Our stackup calculator checks aspect ratio against your smallest drilled hole, and the readiness pre-check flags anything above 10:1 for review and above 12:1 as a likely engineering query.

Put a maximum remaining stub length and the must-not-cut layer on the fabrication drawing. IPC-6012E defines back-drilled holes and stubs (sections 1.4.1, 1.4.2 and 3.3.9) but leaves the stub limit to the procurement documents. The limit follows from the stub's quarter-wave resonance: a 30 mil (0.76 mm) stub in a Dk 3.2 laminate resonates near 55 GHz, right at the 53 GHz Nyquist frequency of 224G PAM4, so 224G channels need stubs well below that. Published fabricator capability varies. One large North American fabricator quotes a nominal stub of about 7 ± 5 mil from the must-not-cut layer in its back-drilling bulletin, and advanced shops report about 4 ± 2 mil. The number you can hold is therefore a fabricator capability to confirm in the stackup review, not a standard value.

Each additional lamination cycle repeats the press, drill, plate and imaging steps for one sub-core. Cost and lead time therefore rise with every cycle, and so does the chance of a registration or yield problem. Repeated press cycles also take the resin through its cure temperature again, so the laminate must be rated for the number of laminations planned. Check the supplier's datasheet or ask the fabricator before committing to a structure. Sequential lamination earns its cost where through-holes cannot do the job: blind and buried vias under fine-pitch packages, and short via stubs on high-speed nets without back-drilling. IPC-2226A describes the HDI via structures. We count the lamination cycles in the stackup review because each one is also a schedule decision.

±10% is the standard controlled-impedance tolerance. Many fabricators offer ±7% or ±5% as a tighter option, at extra cost and with test coupons on every panel. Holding a tighter tolerance needs controlled dielectric thickness (resin content and press), trace-width etch compensation, and a known Dk for the exact construction. The 85 Ω pairs used for PCIe and the 90 Ω and 100 Ω pairs used for Ethernet SerDes are specified the same way. The tolerance applies to the measured coupon, tested by TDR per IPC-TM-650 2.5.5.7A, with IPC-2141A as the design guide. Ask for the impedance test report to ship with the boards.

Specify a local flatness limit over the package site at reflow temperature, agreed with the EMS, in addition to the board's overall bow and twist. The IPC-6012E default of 0.75% for boards with surface-mount parts (section 3.4.3, measured per IPC-TM-650 2.4.22C) allows about 0.6 mm of bow across an 80 mm span, while a board that bows by even 0.2 mm across a package of that size can open solder joints during reflow. Package warpage at temperature is measured per JEDEC JESD22-B112 or JEITA ED-7306, and IPC-9641 gives guidance on board flatness at high temperature. On the material side, low-CTE T-glass in the outer cores under the package is the main lever; see the T-glass guide.

Size copper for current and space conductors for voltage. Current-carrying capacity follows IPC-2152, and 48 V power shelves typically need 2–6 oz copper on several layers with wrap plating on the plated holes. NVIDIA announced an 800 V HVDC architecture for AI data centers in May 2025, with production planned alongside its Kyber rack systems in 2027. At 800 V the current for the same power is far lower, so less copper is needed, but conductor spacing, creepage and insulation become the governing design rules. Spacing follows IPC-2221 together with the safety standard of the end product. Board thickness for these designs is set by the copper and insulation stack, and z-axis expansion on thick boards stays the main reliability risk. See rack power boards.

Production insertion loss is verified on test coupons built on the same panel as the boards, not on the boards themselves. Two IPC method documents cover it. IPC-TM-650 2.5.5.12A covers VNA, SPP, SET2DIL and Delta-L. IPC-TM-650 2.5.5.14 (2021) is a frequency-domain method that incorporates Intel's Delta-L. SET2DIL converts a single-ended TDR measurement into differential insertion loss, which makes it fast enough to screen production lots. Delta-L measures two line lengths and subtracts them to remove probe and via effects, then reports loss per inch at set frequencies. Agree the method, the coupon design, the frequency points and the pass limit on the fabrication drawing; without them there is no loss requirement to inspect against.

At minimum:

• a certificate of conformance naming the fabrication site;
• the electrical test result for every board;
• the impedance test report from TDR coupons;
• microsection reports to the IPC-6012 class on the drawing;
• the insertion loss coupon report, where the drawing sets a loss limit;
• a material declaration naming the laminate, glass style and copper foil.

Programs with origin rules add country-of-origin records for the board, the laminate and the foil. Every Tecsply PCB order ships with the signed stackup, the material declaration, inspection records to the specified IPC-6012 class and country-of-origin records. Additional reports are listed on the drawing or in the purchase order.

Use three tests together:

• Interconnect stress testing (IST, IPC-TM-650 2.6.26A, "DC Current Induced Thermal Cycling Test") heats coupons with DC current. It finds plated-hole and via weaknesses in hours rather than weeks, and it is the usual test for thick boards.
• Thermal shock per IPC-TM-650 2.6.7.2 is part of IPC-6012 Class 3 qualification.
• Convection reflow simulation per IPC-TM-650 2.6.27B shows whether the board survives the number of lead-free reflow passes that assembly and rework will apply.

Add CAF testing per IPC-TM-650 2.6.25C where hole spacing is tight. On a 4–6 mm board the main risk is z-axis expansion stretching the copper barrel, so these tests matter more than on a thin board.

Yes. Conductive anodic filament (CAF) growth becomes more likely as the spacing between plated holes shrinks and as a board spends years powered in a warm, humid data hall. Dense via fields under large AI packages are exactly that case. Specify a CAF-resistant laminate by name and ask for CAF test data per IPC-TM-650 2.6.25C, with IPC-9691B as the user guide for the test. CAF resistance depends on the resin system, the glass finish and the fabricator's drilling and desmear quality together, so the test data should come from the same laminate and a comparable hole pitch.

Commercial server and AI boards are commonly bought to IPC-6012 Class 2, "dedicated service electronic products", plus a customer specification that tightens selected attributes such as plating thickness, annular ring or microsection sampling. Class 3, "high performance/harsh environment electronic products" in IPC-6011A ("high reliability" in earlier revisions), is specified when the program needs continued performance on demand, as in aerospace, defense and some infrastructure equipment. Class 3 adds inspection and microsection requirements and usually cost. The class and any added requirements belong on the fabrication drawing, because the inspection records shipped with the boards are written to that class.

Six things set most of the price:

• The laminate grade and how many layers use it: ultra-low-loss M8-grade material costs more than M6 or M7.
• The layer count and board thickness.
• The number of lamination cycles.
• Drilling: hole count, back-drilling and aspect ratio.
• HDI structures such as stacked microvias.
• The testing written on the drawing: impedance, insertion loss and microsections.

Yield matters as much as any of these, because a 30-layer panel that fails late carries every earlier process step with it. In 2026 material allocation is a further driver. Electronic-grade glass cloth prices rose by more than 100% year on year and CCL by roughly 70%, so moving plane layers to a lower grade and qualifying an alternate laminate both protect price and schedule. See the supply watch.

Tecsply supplies rigid multilayer PCBs from 8 to 40+ layers and up to 6.0 mm finished thickness, as bare boards. Typical starting points are 16–24 layers at 2.4–3.6 mm for AI accelerator baseboards (20–32 layers at 3.2–5.0 mm when the package is larger than 60 mm), 18–28 layers at 3.0–4.5 mm for 800G–1.6T switches, 10–20 layers at 2.0–3.2 mm for avionics and defense boards, and 30–40+ layers up to 6.0 mm for backplanes and midplanes. A build thicker than 6.0 mm goes to an engineering review before it is quoted. Final layer count, thickness and lead time are quoted per stackup.

A backplane carries long channels between connectors across a thick board, so loss, via stubs and plated-hole reliability set the stackup. Our default starting points are an M6-grade laminate (Megtron 6 class) with NE-glass or L-glass in 1078 or 1080 style for 56G PAM4, and an M7-grade laminate (Megtron 7, Tachyon 100G or EM-890K class) with spread NE-glass or L-glass in 1067 or 1078 style for 112G PAM4, with the copper foil grade chosen per channel length. Thick 7628 multi-ply cores carry the planes, which is how 30–40+ layer backplanes reach 5 to 6 mm. On the drawing, state the maximum back-drill stub and the must-not-cut layer for high-speed nets, the impedance targets, and the laminate's z-axis expansion and Td. Plan plated through-holes at about 10:1 aspect ratio, so a 5.0 mm board needs a 0.50 mm drilled hole; higher ratios are confirmed with the fabricator.

Yes, as bare boards built to your stackup and drawing, within the same 8 to 40+ layer, up to 6.0 mm envelope as our other high-layer-count PCBs. Test boards combine dense, fine-pitch device fields that need HDI or sequential lamination for breakout, thick constructions where aspect ratio decides which drill sizes are realistic, controlled impedance on high-speed paths, and flatness across the device area. Send the stackup, the drill table with the smallest drilled hole, impedance targets and flatness requirements; aspect ratios above about 10:1 are reviewed with the fabricator before the quote. Tecsply does not assemble boards: components, sockets and hardware are fitted by your EMS or test-hardware assembler.

For a prototype, send Gerber or ODB++ files, the fabrication drawing, the stackup (laminate, glass style and copper weight per layer, or the targets to build to), the drill table with back-drill and via structures, impedance targets, IPC-6012 class, surface finish, the fastest lane rate and largest package, quantity and required date. For high volume, add annual volume and release quantities, the panel or array drawing, the test and report requirements written on the drawing, packaging, the delivery point for the DDP price, and the country of manufacture you require. Every Tecsply product, from multilayer PCBs to machined metal parts, is manufactured in a non-restricted country specified by the customer. Lead time is quoted per stackup. Do not send ITAR-controlled technical data; Tecsply cannot accept it today.

Not today. Tecsply cannot accept ITAR-controlled technical data, so please do not send ITAR-controlled drawings, Gerbers, stackups or specifications through the website, by email or by any other channel. For a defense program whose board data is not export-controlled, we quote through the normal process, with country-of-origin records for the board, the laminate and the copper foil. Every Tecsply product, from multilayer PCBs to machined metal parts, is manufactured in a non-restricted country specified by the customer.

Aerospace and defense multilayer PCBs are usually built and inspected to IPC-6012 Class 3 or 3A, which includes 100 thermal-shock cycles per IPC-TM-650 2.6.7.2 on test coupons. They use high-Tg (170 °C and above) or polyimide laminates, often against program-specified thermal cycling between −55 °C and +125 °C, require CAF-resistant materials, and increasingly need country-of-origin traceability. From January 1, 2027, 10 U.S.C. 4873 bars the Department of Defense from acquiring covered PCBs from North Korea, China, Russia or Iran.

High-Tg FR-4 with Tg of 170 °C or above, Td of 340 °C or above and total z-axis expansion below 3% (50–260 °C) covers most avionics and defense boards, including boards that will see lead-free rework. Polyimide laminates, with Tg of 250 °C and above, are specified when the operating envelope passes 200 °C, and are a common choice for Class 3A satellite and space payload boards. Polyimide costs more and is harder to process, so we recommend it only when the thermal envelope requires it.

From January 1, 2027, 10 U.S.C. 4873 bars the Department of Defense from acquiring a covered printed circuit board from a covered nation: North Korea, China, Russia or Iran. The advance notice of proposed rulemaking of July 2, 2026 (comments closed August 31, 2026) proposes to test where bare and partially manufactured boards are fabricated, backed by an Independent Hardware Assurance Framework built on ISO/IEC 20243, IPC-1782 (traceability) and IPC-1791 (trusted designer, fabricator and assembler), with certifications flowed down to every subcontract tier.

In practice a prime contractor needs to show where the bare board was fabricated, trace the laminate and copper foil lots behind it, and hold certifications from every tier. Every Tecsply product, from multilayer PCBs to machined metal parts, is manufactured in a non-restricted country specified by the customer, outside the four covered nations; boards come from partner fabricators in Taiwan, Japan, Thailand, Vietnam and Malaysia. Aerospace and defense orders ship with origin records for the board, the laminate and the foil. Whether a specific program is a covered system, and the final certification requirements, are set by the statute and the final DFARS rule; confirm them with your contracting officer.

It can. 10 U.S.C. 4873 and the July 2026 advance notice of proposed rulemaking focus on where the bare board is fabricated, but prime contractors increasingly ask for traceability of the laminate and copper foil behind the board, and much of the world's standard-grade foil capacity is in mainland China. High-end HVLP foil comes mainly from Japanese, Taiwanese and Luxembourg producers.

For aerospace and defense orders we record the foil product, lot and country of origin on the material declaration alongside the laminate lot, so the origin package covers the board, the laminate and the foil. Whether a specific program requires material-level origin is set by the contract; confirm it with your contracting officer.

Every Tecsply product, from multilayer PCBs to machined metal parts, is manufactured in a non-restricted country specified by the customer, outside North Korea, China, Russia and Iran, and the manufacturing site is named on the certificate of conformance. Boards come from partner fabricators in Taiwan, Japan, Thailand, Vietnam and Malaysia.

For titanium and nickel alloys under DFARS 252.225-7009, the melt source is confirmed in each quote and the mill certificate travels with each lot.

AI server demand for high-layer-count boards is consuming glass cloth and copper foil capacity. Electronic-grade glass cloth prices rose by more than 100% year on year in 2026 and CCL by roughly 70%, with high-speed laminate production lead times stretching from 12–18 days to 18–25 days. Industry outlooks expect capacity relief to begin only in late 2027. We lock material allocation with our fabricators on framework agreements rather than order by order.

As of September 2026, PCBs of Taiwan origin enter the US at a combined rate of about 10%, Japan origin at about 12.5% (the Section 301 duty tops the MFN rate up to 12.5%), and Thailand origin at MFN plus 12.5%. China-origin boards carry the 25% Section 301 duty plus a further 12.5%, and the remaining Section 301 exclusions covering bare boards expire on November 10, 2026. Rates change frequently; we quote DDP with a documented tariff-adjustment clause. Vietnam- and Malaysia-origin rates are confirmed on each quote.

Tecsply works with partner fabricators in Taiwan, Japan, Thailand, Vietnam and Malaysia so that a US program has more than one qualified source located outside the four 10 U.S.C. 4873 covered nations. Taiwan partners form the core of the network for high-layer-count and HDI builds; Japanese partners add an origin next to the makers of much of the high-end laminate, glass cloth and HVLP copper foil; Southeast Asian partners add capacity and a further origin when AI server demand is absorbing high-layer-count capacity and tariff rates move between origins. Which partner builds a given board is decided by its qualified capability for that stackup, not by price alone.

An engineering query is a written question a PCB fabricator sends the customer during the pre-production CAM review when the files conflict, are incomplete, or contain a feature that cannot be built as drawn. The fabricator does not guess the designer's intent: typical EQs cover a missing outline or drill file, unclear plated and non-plated holes, a stackup that does not match the drill spans, or features below the fabricator's limits. Each open EQ delays the quote or the build until it is answered, so a complete first submission saves days.

No. The pre-check reads the files with your browser's File API and analyses them on your own computer; no file content is sent to Tecsply or to any other server. That keeps ITAR-controlled and CUI design data under your control. To get a quote, send the files through your normal controlled channel; the pre-check report can travel with them.

The Thermal, Enclosures & Aerospace Machining division of Tecsply Inc supplies custom metal hardware made to a customer's drawing in three families: thermal management parts (custom heat sinks, liquid cold plates and coolant manifolds), enclosures and chassis (server, power-shelf, PDU, rack-mount and rugged edge-computing enclosures, computer cases and stamped galvanized-steel enclosures, plus copper busbars), and aerospace parts machined from titanium, aluminum-lithium and nickel superalloys. It is a separate division from Tecsply's PCB business, with its own engineering review, quoting and quality records.

Yes. Tecsply's Thermal, Enclosures & Aerospace Machining division supplies metal enclosures stamped from galvanized steel sheet, and computer cases, built to the customer's drawing. Send the drawing, sheet grade and thickness, coating, outside finish and expected annual volume; the volume decides how the stamped part is tooled.

Yes. When a program needs them together, the heat sink or cold plate, the enclosure and the copper busbars are delivered as one mechanical subassembly under one part number, fitted and inspected before it ships, so the receiving line installs one item instead of reconciling tolerances between three suppliers. Each part can also be ordered on its own.

No. PCBs are quoted separately by Tecsply's PCB division. Bare boards ship to the customer's EMS for SMT and through-hole assembly, while the mechanical subassembly ships to the system integration line, and the two are usually specified by different engineers and bought by different commodity teams. Each therefore gets its own quote, drawing revision and inspection record; one Tecsply contact can coordinate both when the same program needs them.

Yes. Under DFARS 252.225-7009, titanium and titanium alloys, and nickel alloys with more than 10% alloying metals, are specialty metals that must be melted or produced in the United States or a qualifying country when they are delivered in US defense contracts. The qualifying-country list in DFARS 225.003 includes Japan, Germany, the United Kingdom and 25 other countries, but not Taiwan.

For DFARS programs, titanium and nickel-alloy material therefore has to come from mills in the United States or a qualifying country; Tecsply confirms the melt source in each quote, and the mill certificate showing the melt location travels with each lot; machining can be done by a qualified partner elsewhere. Aluminum-lithium alloys are not specialty metals under this clause. Exceptions such as the 2% de minimis threshold are confirmed program by program.

Use aluminum-lithium when weight or stiffness limits the design. Each 1 wt% of lithium lowers density by about 3% and raises elastic modulus by about 6%; alloy 2050, for example, matches or exceeds 7050-T7451 in tensile and fracture properties with about 4% lower density and up to 5% higher modulus. Al-Li costs more than 2xxx and 7xxx alloys, so it is usually reserved for weight-critical structure such as launch-vehicle tanks, fuselage and wing structure, and spacecraft primary structure.

It depends on tolerance and cost. Solution-treated Inconel 718 (AMS 5662) is softer and machines faster, but the part changes dimension slightly when it is aged afterwards, so tight features may need finishing after aging. Solution-treated-and-aged material (AMS 5663) is delivered at service hardness and holds its dimensions, but machining is slower and tool wear is higher. Tecsply agrees the condition and the machining and heat-treat sequence with the customer before quoting.