Engineering tool
PCB production-readiness pre-check
Check a Gerber file set of any layer count before you send it for a quote, from a 4-layer board to a 30-plus-layer AI baseboard or a 90-layer build: missing layers, gaps in the copper layer sequence, drill files, netlist and fabrication notes, plus the board size, layer count, finest copper feature, smallest drill and aspect ratio a CAM engineer will look at first. Your files are read by your own browser and are never uploaded.
Your files never leave your computer
The pre-check reads Gerber, Excellon and IPC-D-356 files with your browser's File API and analyses them locally; nothing is sent to Tecsply or anyone else, which keeps ITAR-controlled and CUI design data under your control. A quote still needs the files, sent through your normal controlled channel.
1 · Select the fabrication files
Reading files…
2 · What is checked
- Tier 1, completeness: copper, solder mask, legend and outline layers; gaps in the copper layer sequence, read from Gerber X2 layer numbers; drill files and plated / non-plated split; netlist; fabrication notes.
- Tier 2, specification: layer count, board size, finest drawn copper feature, smallest drill, hole count and plated-hole aspect ratio.
- Left to the engineer: spacing and annular-ring rules, netlist comparison, stackup and impedance, material availability.
Tip: the samples are synthetic boards with Gerber X2 attributes. The 32- and 90-layer samples show how aspect ratios above 12:1, common on high-layer-count builds, are flagged for the engineering review.
Readiness report
Tier 1 · File-set completeness
| Status | Item | Detail |
|---|
Tier 2 · Specification summary
| Status | Item | Detail |
|---|
Files identified
| File | Identified as | How | Units |
|---|
Report text
What the pre-check covers
A fabricator's pre-production review has 4 layers of checks, and this tool automates the first 2: file-set completeness and the specification summary. The other 2, geometry rule checks and engineering judgement, stay with a CAM engineer, who raises an engineering query (EQ) for anything that cannot be built as drawn rather than guessing the designer's intent.
| Layer | What is checked | In this tool |
|---|---|---|
| 1 · File completeness | Copper, mask, legend and outline Gerbers; a continuous copper layer sequence; drill files with plated / non-plated split; netlist; stackup and fabrication notes | Yes |
| 2 · Specification summary | Board size, layer count, finest copper feature, smallest drill, hole count, aspect ratio, blind / buried via spans | Yes, except via spans |
| 3 · Geometry rules | Trace spacing, annular ring, solder-mask dams, slivers, acid traps, copper-to-edge and hole-to-copper clearance | No, CAM engineer |
| 4 · Engineering judgement | Stackup and impedance feasibility, drill-span versus stackup, IPC-D-356 netlist comparison, material availability | No, CAM engineer |
How results are classified
Every item gets 1 of 5 statuses: OK, Info, Review, Likely EQ or Missing, and the overall result takes the most serious one. "Missing" means a file the fabricator needs is absent; "Review" and "Likely EQ" mean the fabricator will ask about the item before building. The pre-check reports measured values and common review triggers, such as copper features below 0.1 mm, drills below 0.2 mm and aspect ratios above 10:1 and 12:1; it does not judge whether a specific fabricator can build the board, which is decided in the engineering review.
How files are read
The pre-check reads RS-274X Gerber (including Gerber X2 layer attributes), Excellon drill files in inch or metric, IPC-D-356 netlists and ZIP archives. There is no limit on layer count. Layers are identified from Gerber X2 file-function attributes first, then from the naming conventions of KiCad, Altium, Eagle and other EDA tools, then from file content. When every inner layer carries a layer number, from Gerber X2 attributes or KiCad-style In1_Cu names, the pre-check confirms that the sequence from L1 to the bottom layer has no gaps, the most common way a 30-plus-layer set goes out incomplete. Board size comes from the outline layer; the finest copper feature is the smallest round aperture used to draw on a copper layer, so a thin outline or text stroke on copper can set it. ODB++ and IPC-2581 archives are not read yet; send those directly for review.
From pre-check to quote
A Tecsply quote is prepared by an engineer, usually within five business days, from the full file set and your stackup, class and volume. The pre-check shortens that review by making sure the first submission is complete; "Request a quote with this report" carries the summary into the quote form, and the files follow through your normal controlled channel.
Pre-check FAQ
Two questions engineers ask before trusting a web tool with a Gerber set.
What is an engineering query (EQ) in PCB fabrication?
An engineering query is a written question a PCB fabricator sends the customer during the pre-production CAM review when the files conflict, are incomplete, or contain a feature that cannot be built as drawn. The fabricator does not guess the designer's intent: typical EQs cover a missing outline or drill file, unclear plated and non-plated holes, a stackup that does not match the drill spans, or features below the fabricator's limits. Each open EQ delays the quote or the build until it is answered, so a complete first submission saves days.
Are my Gerber files uploaded when I use the readiness pre-check?
No. The pre-check reads the files with your browser's File API and analyses them on your own computer; no file content is sent to Tecsply or to any other server. That keeps ITAR-controlled and CUI design data under your control. To get a quote, send the files through your normal controlled channel; the pre-check report can travel with them.
References
- Ucamco, The Gerber Layer Format Specification (RS-274X and Gerber X2 attributes).
- IPC-D-356, Bare Substrate Electrical Test Data Format (netlist).
- PCB fabricator CAM and engineering-query practice: PCBMay "Engineering Questions and CAM Checklist"; HilPCB "Gerber Data Preparation for Reliable PCB Fabrication"; Westak "IPC-D-356A Netlist".
- Layer-naming conventions and parsers tested against open-source board files from the tracespace project (Arduino Uno and clockblock, CC BY-SA; McHCK, CERN OHL).